Possibilities and Limitations of CMOS Technology for the Production of Various Microelectronic Systems and Devices

In this analytical review, we consider the fundamental laws of the development of planar CMOS technology (a technology based on the use of complementary field-effect MOSFETs formed by metal, oxide, and semiconductor layers) over the past 50 years. We show the possibilities and limitations of the geo...

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Bibliographic Details
Published in:Nanobiotechnology Reports (Online) 2022-02, Vol.17 (1), p.24-38
Main Authors: Bespalov, V. A., Dyuzhev, N. A., Kireev, V. Yu
Format: Article
Language:English
Subjects:
Ambient intelligence
Chemistry and Materials Science
CMOS
Crystals
Industrial and Production Engineering
Machines
Manufacturing
Materials Science
Mechanical properties
Membrane structures
Microelectronics
Moore's law
MOSFETs
Nanotechnology
Norms
Processes
Reviews
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Summary:In this analytical review, we consider the fundamental laws of the development of planar CMOS technology (a technology based on the use of complementary field-effect MOSFETs formed by metal, oxide, and semiconductor layers) over the past 50 years. We show the possibilities and limitations of the geometric and equivalent scaling of planar and fin MOSFETs. The basic standards of CMOS technology for various devices and at various stages of its development are given. We make a distinction between the technological and design-topological norms in CMOS technology. The economic and technical limits of Moore’s Law for planar CMOS technology and the technological limit of its development over the past decade are shown. It is proved that in the next 30 years, the main direction in the development of microelectronic-device technology will be the direction called “More than Moore.” This direction is associated with the creation of numerous systems of ambient intelligence based on processes of the heterogeneous three-dimensional (volumetric) integration of various microchips. In this case, the best option is to arrange microcircuit crystals in stacks (packs) and connect them with vertical wires passing through silicon crystals and interconnecting boards. We note that in the case of the vertical assembly of crystals in the process of heterogeneous integration, most crystals with devices and through holes will have a thickness of less than 50 μm, which will require the study of the mechanical properties and strength of such membrane structures.
ISSN:2635-1676
1995-0780
2635-1684
1995-0799
DOI:10.1134/S2635167622010037