A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application

Static random access memory is a key component for most microprocessor-based digital devices. With the declining technology node and reducing supply voltage, it is essential to improve its performance. This paper proposes a seven transistor, single-ended, bit cell configuration. The performance of t...

Full description

Saved in:
Bibliographic Details
Published in:Circuits, systems, and signal processing systems, and signal processing, 2022-05, Vol.41 (5), p.2779-2801
Main Authors: Rawat, Bhawna, Mittal, Poornima
Format: Article
Language:English
Subjects:
Circuits and Systems
Configuration management
Electrical Engineering
Electronics and Microelectronics
Engineering
Instrumentation
Layouts
Low voltage
Power consumption
Pulse duration
Random access memory
Signal,Image and Speech Processing
Static random access memory
Transistors
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Static random access memory is a key component for most microprocessor-based digital devices. With the declining technology node and reducing supply voltage, it is essential to improve its performance. This paper proposes a seven transistor, single-ended, bit cell configuration. The performance of the cell are evaluated at 300 mV supply voltage. The hold/read noise margins for the proposed bit cell is fairly high at 98 mV each, while the write margin is 154 mV. The reliability of the cell is measured using Monte Carlo process variation and temperature variation analysis. The results obtained for the proposed cell are compared against various pre-existing 5T, 6T, 7T, and 8T cells to showcase the improvements achieved by the proposed 7T cell. The power consumption for the proposed cell is minimal amongst others and requires a pulse width of 13 and 5 ns to perform successful write and read operations, respectively. The above-stated enhancement is achieved for the layout area of 0.65 μm 2 . While the layout footprint for 5T, 6T1, 6T2, 7T1, 7T2, 7T3, 8T1, 8T2, and 10T cell are 0.66, 0.82, 0.048, 0.74, 0.82, 0.8, 0.84, 1.34, and 1.27 µm 2 , respectively.
ISSN:0278-081X
1531-5878
DOI:10.1007/s00034-021-01912-5