Self-heating effect on logic performance of 6T-SRAM based on CFET device

Abstract Complementary FET (CFET) devices have become emerging and promising candidates for continuing Moore’s law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to...

Full description

Saved in:
Bibliographic Details
Published in:Japanese Journal of Applied Physics 2022-05, Vol.61 (SC), p.SC1010
Main Authors: Zhao, Songhan, He, Yandong, Liu, Xiaoyan, Du, Gang
Format: Article
Language:English
Subjects:
6T-SRAM
Complementary FET (CFET)
Heating
High temperature effects
Performance evaluation
Self-Heating
Static random access memory
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Abstract Complementary FET (CFET) devices have become emerging and promising candidates for continuing Moore’s law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the static random-access memory (SRAM) unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.
ISSN:0021-4922
1347-4065
DOI:10.35848/1347-4065/ac3c1b