Hardware Support to Minimize the End-to-End Delay in Ethernet-Based Ring Networks

Ethernet is a popular networking technology in factory automation and industrial embedded systems, frequently using a ring topology for improved fault-tolerance. As many applications demand ever shorter cycle times and a higher number of nodes, the popular ring endure to remain as a valid topology....

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Bibliographic Details
Published in:Electronics (Basel) 2019-10, Vol.8 (10), p.1097
Main Authors: P. Corrêa, Tomás, Almeida, Luis
Format: Article
Language:English
Subjects:
Accelerators
Access control
Communication
Cycle time
Delay
Design
Ethernet
Fault tolerance
Field programmable gate arrays
Hardware
Influence
Network topologies
Nodes
Rings (mathematics)
Wireless networks
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Summary:Ethernet is a popular networking technology in factory automation and industrial embedded systems, frequently using a ring topology for improved fault-tolerance. As many applications demand ever shorter cycle times and a higher number of nodes, the popular ring endure to remain as a valid topology. In this work, we discuss the factors that determine the ring network delay and show how they affect the network cycle time. Since increasing the link capacity has limited reach, we explore a time-triggered protocol that brings the nodes forwarding delay near to the physical layer delay. Additionally, we propose hardware accelerators based on FPGA technology that minimise the packet reception delay from physical reception to delivery to an application handler, preserving Ethernet layers and being compatible with its standard. This paper explains the accelerators concept and implementation, presents measurements using standard Media Access Control implementations, and shows the solution effectiveness with experimental results. We achieved a delay, from physical reception to the triggering of a user-level handler, of 1.1 µs independent of the packet length.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics8101097