All‐Solid‐State Ion Synaptic Transistor for Wafer‐Scale Integration with Electrolyte of a Nanoscale Thickness

Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For i...

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Bibliographic Details
Published in:Advanced functional materials 2021-06, Vol.31 (23), p.n/a
Main Authors: Yu, Ji‐Man, Lee, Chungryeol, Kim, Da‐Jin, Park, Hongkeun, Han, Joon‐Kyu, Hur, Jae, Kim, Jin‐Ki, Kim, Myung‐Su, Seo, Myungsoo, Im, Sung Gap, Choi, Yang‐Kyu
Format: Article
Language:English
Subjects:
all solid state
Artificial neural networks
Chemical vapor deposition
CMOS
Computation
deep neural network
Electrolytes
electrolyte‐gated synaptic transistor
Handwriting
Hardware
initiated chemical vapor deposition
Materials science
Multilayer perceptrons
Parallel processing
polyethylene glycol di‐methacrylate
Power consumption
Power management
Resistance
Semiconductor devices
Silicon wafers
Symmetry
synaptic devices
Transistors
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Summary:Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with a large number of conductance levels is required. Here, an all‐solid‐state polymer electrolyte‐gated synaptic transistor (pEGST) is fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition process. The pEGST shows good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ pulse−1. Selected 128 levels from 8,192 are used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7%. An all‐solid‐state polymer electrolyte‐gated synaptic transistor (pEGST) is fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition process. The pEGST shows good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ pulse−1.
ISSN:1616-301X
1616-3028
DOI:10.1002/adfm.202010971