A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction

This letter presents a highly digital, technology scalable, and energy-efficient cryptographic-quality true random number generator (TRNG). The proposed architecture presents a balanced approach to TRNG design, relying on a simpler, noncryptographic quality physical random number generator ( phy RNG...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2018-12, Vol.1 (12), p.237-240
Main Authors: Pamula, Venkata Rajesh, Sun, Xun, Kim, Sung Min, Rahman, Fahim ur, Zhang, Baosen, Sathe, Visvesh S.
Format: Article
Language:English
Subjects:
Bias
Bit rate
CMOS
Correlation
Cryptographic-quality
Cryptography
Entropy
Generators
information security
iterative von Neumann (IVN)
Markov chain (MC)
Markov processes
metastability
NIST
Numbers
Post-processing
Random numbers
true random number generators (TRNGs)
Voltage measurement
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Summary:This letter presents a highly digital, technology scalable, and energy-efficient cryptographic-quality true random number generator (TRNG). The proposed architecture presents a balanced approach to TRNG design, relying on a simpler, noncryptographic quality physical random number generator ( phy RNG) combined with energy-efficient integrated post-processing to de-correlate and de-bias the phy RNG bitstream. Operating at a supply voltage ( {V}_{\text {dd}}) of 0.53 V, a 65-nm CMOS prototype of the TRNG achieves a peak energy-efficiency of 2.58 pJ/bit. TRNG bitstreams pass all NIST randomness benchmarks over a {V}_{\text {dd}} range of 0.5-1.05 V across −20 °C-100 °C, demonstrating its efficacy and robust operation over a wide {V}_{\text {dd}} and temperature range.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2019.2896777