Carrier Lifetime Measurement in Ultrathin FD-SOI Using Virtual Diodes

In ultrathin fully depleted SOI PIN structures with underlapped gate, the front and back gates can be biased such as to emulate electrostatic diodes. The gate-induced electrons and holes result in a virtual P-N junction in the center of an undoped body. The current-voltage I - V curves are essential...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2019-04, Vol.66 (4), p.1874-1880
Main Authors: Lee, Kyung Hwa, Park, Hyung-Jin, Bawedin, Maryline, Cristoloveanu, Sorin
Format: Article
Language:English
Subjects:
Carrier lifetime
Charge carrier lifetime
Current measurement
Doping
Electric potential
electrostatic doping
Logic gates
P-i-n diodes
P-N diode
P-n junctions
PIN diodes
Service life assessment
Silicon
silicon-on-insulator (SOI)
virtual diode
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Summary:In ultrathin fully depleted SOI PIN structures with underlapped gate, the front and back gates can be biased such as to emulate electrostatic diodes. The gate-induced electrons and holes result in a virtual P-N junction in the center of an undoped body. The current-voltage I - V curves are essentially diode-like but reconfigurable via gate voltage tuning. The virtual P-N and P-I-N diodes are used, for the first time, to evaluate the carrier lifetime in ultrathin SOI layers. This paper presents novel experiments and simulations. The transition between recombination and diffusion current in I - V characteristics enables quick lifetime extraction. A more evolved and accurate technique consists in monitoring the reverse recovery current in virtual diodes. This method reveals a very short carrier lifetime in 7-nm-thick SOI layers where surface recombination prevails. This result is confirmed by adapting a P-I-N-diode technique to sub-10 nm films.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2019.2897502