A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL) featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the process-voltage-temperature variations of the voltage-controlled oscillator (VCO) frequency. Such FTL utilizes a digit...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits 2019-01, Vol.54 (1), p.88-98
Main Authors:	Yang, Shiheng, Yin, Jun, Mak, Pui-In, Martins, Rui P.
Format:	Article
Language:	eng
Subjects:	Clock multiplier Clocks CMOS Delay lines Delays digital-controlled delay line (DCDL) Electric potential Error detection Frequency division multiplexing Frequency locked loops frequency-tracking loop (FTL) injection-locked phase-locked loop (IL-PLL) Jitter Multiplexing multiplying delay-locked loop (MDLL) phase noise Power consumption ring voltage-controlled oscillator (RVCO) root-mean-square (rms) jitter State of the art Tracking Tuning Vibration Voltage controlled oscillators
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Summary:	This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL) featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the process-voltage-temperature variations of the voltage-controlled oscillator (VCO) frequency. Such FTL utilizes a digital-controlled delay line (DCDL)-based low-power time-interval comparator and an adjacent-edge selector, to precisely detect the static phase offset (SPO) caused by the VCO frequency drifting in the presence of reference injection. The block-sharing-based SPO detection aids nullifying the circuit-mismatch- and offset-induced deterministic error. Also, for the adjacent edge selector, block sharing between its control generation circuits and the coarse FTL further reduces the power consumption. The varactor-tuned dual multiplexed-ring VCOs (MRVCOs) serve to reduce jitter variation while extending the frequency tuning range. Fabricated in a 28-nm CMOS with a core area of 0.0056 mm 2 , the proposed MDLL covers a tuning range from 1.55 to 3.35 GHz, and exhibits a root-mean-square (rms) jitter of 292 fs at 3-GHz output, under a 200-MHz reference clock. The power consumption is 1.45 mW at a 0.8-V supply, resulting in an FoM of −249 dB favorably comparable with the state of the art.
ISSN:	0018-9200 1558-173X