An Area Efficient and Low Power Consumption of Run Time Digital System Based on Dynamic Partial Reconfiguration

Digital signal processing besides multimedia applications needs plenty of data, real-time processing capacity, and high computational power. Thus, adaptable architectures with run-time reconfiguration abilities have gotten expanded consideration. Basically, Reconfiguration computing is going towards...

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Bibliographic Details
Published in:International journal of parallel programming 2020-06, Vol.48 (3), p.431-446
Main Authors: Saravana Ram, R., Gopi Saminathan, A., Arun Prakash, S.
Format: Article
Language:English
Subjects:
Arrays
Computer Science
Digital signal processing
Field programmable gate arrays
Gate arrays
Modules
Multimedia
Power consumption
Processor Architectures
Programmable logic arrays
Reconfiguration
Run time (computers)
Software Engineering/Programming and Operating Systems
Special Issue on Emerging Technology for Software Defined Network Enabled Internet of Things
Strategy
Theory of Computation
Time multiplexing
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Summary:Digital signal processing besides multimedia applications needs plenty of data, real-time processing capacity, and high computational power. Thus, adaptable architectures with run-time reconfiguration abilities have gotten expanded consideration. Basically, Reconfiguration computing is going towards advancing the application adaptability at runtime. A reconfigurable structure can be attained by working up the strategy aimed at configuring an array of programmable logic reprogramming. Field Programmable Gate Arrays (FPGAs) is made with the intention of reconfiguring the array system with interconnects as well as the configuration of logic blocks. To implement a high-performance FPGA device and also to enhance, the given paper proposes a proficient design strategy. The proposed strategy count upon the employment of dynamic partial reconfiguration (DPR) to drive from one mode then onto the next utilizing time-multiplexing on the same chip region. Furthermore, reconfigure modules to spare considerable area and enable the low-cost FPGAs usage. In the given work, reconfigurations of the modules accompanied by the memory are finished. The DPR is implemented betwixt these modes to shift from one mode then onto the next. The proposed method helps in diverse applications with various demands and also attains high performance, power consumption together with throughput. The proposed work gives improved performance with fewer powers and less area utilization which is illustrated by the Experimental outcomes.
ISSN:0885-7458
1573-7640
DOI:10.1007/s10766-018-0578-6