Fixed-Latency Gigabit Serial Links in a Xilinx FPGA for the Upgrade of the Muon Spectrometer at the ATLAS Experiment

We present an implementation of fixed-latency gigabit serial links in a low-cost Xilinx field-programmable gate array. The implementation is targeted for a data packet router in the upgrade of the ATLAS muon spectrometer. The router serves as a packet switch. It handles up to 12 serial inputs at 4.8...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2018-01, Vol.65 (1), p.656-664
Main Authors: Jinhong Wang, Xueye Hu, Pinkham, Reid, Suen Hou, Schwarz, Thomas, Junjie Zhu, Chapman, J. W., Bing Zhou
Format: Article
Language:English
Subjects:
Clocks
Detectors
Fabrics
Field programmable gate arrays
field-programmable gate array (FPGA)
fixed latency
Information processing
Latency
Multiplexing
Optical transmitters
Payloads
serial link
Transceivers
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We present an implementation of fixed-latency gigabit serial links in a low-cost Xilinx field-programmable gate array. The implementation is targeted for a data packet router in the upgrade of the ATLAS muon spectrometer. The router serves as a packet switch. It handles up to 12 serial inputs at 4.8 Gbps from on-detector electronics and four 4.8-Gbps outputs to the trigger processing circuits. The input serial streams are deserialized and aligned to a common clock domain for NULL suppression and data packet forwarding. Gigabit transceivers are used in the processing, and a scheme is developed to maintain low and fixed-latency packet multiplexing through the router. We analyze the latency of the scheme and demonstrate its performance in a setup similar to that of the final detector arrangement.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2017.2784411