Networks on chips: a new SoC paradigm

On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommuni...

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Bibliographic Details
Published in:Computer (Long Beach, Calif.) Calif.), 2002-01, Vol.35 (1), p.70-78
Main Authors: Benini, L., De Micheli, G.
Format: Article
Language:English
Subjects:
Consumer electronics
Design engineering
Design methodology
Designers
Electronics
Electronics industry
Engines
Fasteners
Focusing
Integrated circuits
Mathematical models
Methodology
Modular
Multimedia systems
Network-on-a-chip
Networks
Process design
Semiconductors
System on chip
System-on-a-chip
Telecommunication network reliability
Time to market
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Summary:On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.
ISSN:0018-9162
1558-0814
DOI:10.1109/2.976921