Low Energy Proton SEUs in 32-nm SOI SRAMs at Low Vdd

Near-threshold computing and scaling are combined to operate SRAMs in regions where they are close to being unstable. One consequence of this is an increase in single event upsets (SEUs), due to the minimal charge stored on nodes during reduced voltage operation. In this paper, both modeling and mea...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2017-03, Vol.64 (3), p.999-1005
Main Authors: Rodbell, Kenneth P., Gordon, Michael S., Stawiasz, Kevin G., Oldiges, Phil, Lilja, Klas, Turowski, Marek
Format: Article
Language:English
Subjects:
32-nm silicon on insulator (SOI) SRAM
Computational modeling
Energy
low energy proton (LEP) testing
near-threshold computing
Nodes
proton and heavy ion modeling
Protons
Scaling
Semiconductor process modeling
SEU critical charge (QCRIT)
Silicon
Silicon-on-insulator
single event upset (SEU)
Single event upsets
SOI (semiconductors)
SOI technology
Transistors
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Summary:Near-threshold computing and scaling are combined to operate SRAMs in regions where they are close to being unstable. One consequence of this is an increase in single event upsets (SEUs), due to the minimal charge stored on nodes during reduced voltage operation. In this paper, both modeling and measurements [with heavy ions, MeV and low energy protons (LEPs)] are reported for a 32-nm silicon on insulator SRAM, over a range of 0.4-1.05 V. The results show that the SEU rate increases by 3X at low-supply voltages, where very LEPs are able to upset these devices. This can be a reliability concern when running SRAMs at near-threshold voltages in LEP space environments.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2017.2659382