Digital Offset Cancellation for Long Time-Constant Subthreshold OTA-C Integrators

Systems using integrators with very long time constants can place a severe constraint on allowable amplifier offset. Postfabrication cancellation of these offsets is a requirement in these applications. This brief describes the design, simulation, and measurement of a subthreshold operational transc...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2015-11, Vol.62 (11), p.1038-1042
Main Authors: White, Daniel J., Hoffman, Michael W., Balkır, Sina
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Algorithms
Analog processing circuits
Calibration
Calibration algorithms
Cancellation
Computer simulation
Digital
Integrator
Integrators
Mirrors
Mixed analog digital integrated circuits
Offsets
Operational amplifiers
OTA
Prototypes
Sub-threshold
Transistors
Tuning
Citations: Items that this one cites
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Summary:Systems using integrators with very long time constants can place a severe constraint on allowable amplifier offset. Postfabrication cancellation of these offsets is a requirement in these applications. This brief describes the design, simulation, and measurement of a subthreshold operational transconductance amplifier (OTA) with digital calibration and its robust calibration algorithm. Statistical simulations show the scheme's ability to reduce the output offset by a factor of 40. Measurements on many prototype OTAs validate the technique's ability to bring the standard deviation of integrated output offset to less than 10 mV in most cases, or about 30μ V input-referred offsets. A secant-based algorithm is proposed that finds the optimum digital calibration code for each OTA in a small number of search steps that minimizes the integrated output offset. This algorithm is robust to nonmonotonic tuning characteristics, allowing the additional circuitry to be minimally sized. For low-frequency applications below 5 Hz, the scheme has nearly no net impact on die area in processes allowing circuitry below the integration capacitor.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2015.2455982