Vertical GAAFETs for the Ultimate CMOS Scaling

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated tha...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2015-05, Vol.62 (5), p.1433-1439
Main Authors: Yakimets, Dmitry, Eneman, Geert, Schuddinck, Pieter, Trong Huynh Bao, Bardon, Marie Garcia, Raghavan, Praveen, Veloso, Anabela, Collaert, Nadine, Mercha, Abdelkarim, Verkest, Diederik, Voon-Yew Thean, Aaron, De Meyer, Kristin
Format: Article
Language:English
Subjects:
Accounting
Capacitance
CMOS
Design technology cooptimization
Devices
Electrodes
Energy consumption
FinFET
FinFETs
Interconnections
Layout
Logic gates
nanowire (NW)
Oscillators
Performance evaluation
Power consumption
Resistance
scaling
Switches
vertical gate-all-around FET (VFET)
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Summary:In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2015.2414924