Optimization of Latency Insensitive Systems Through Back Pressure Minimization

In modern System on Chip (SoC) designs, the multi-cycle delays on long interconnects between synchronously clocked IP blocks are accommodated by latency insensitive protocols (LIP) through extra valid/stall handshakes between components and additional logic blocks called relay stations. The use of h...

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Bibliographic Details
Published in:IEEE transactions on computers 2015-02, Vol.64 (2), p.464-476
Main Authors: Xue, Bin, Shukla, Sandeep K., Ravi, S. S.
Format: Article
Language:English
Subjects:
Algorithms
back pressure
buffer sizes
Clocks
Computational modeling
Design engineering
Gold
Graphs
Interconnections
IP networks
Latency insensitive system
Linear programming
Minimum cost
Optimization
Relay stations
Schedules
Stall
System on chip
Throughput
Trouble shooting
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Summary:In modern System on Chip (SoC) designs, the multi-cycle delays on long interconnects between synchronously clocked IP blocks are accommodated by latency insensitive protocols (LIP) through extra valid/stall handshakes between components and additional logic blocks called relay stations. The use of handshaking interconnects and relay stations leads to area and latency penalties, that must be minimized for cost effective SoC designs. Interconnected IP blocks with certain graph topology have periodic behaviors that can be exploited to remove the need for handshake interconnects. Unfortunately, the periodic schedule may not exist for any LIS designs consist of two or more strongly connected components. Some of these systems are not bounded without back pressure. In the past, back pressure between SCCs has always been implemented as stall signals in the backward direction, and they are required to prevent overflow. In this paper, we propose an LIS design optimization algorithm which computes a minimum set of back pressure arcs required between SCCs. We model an LIS by a partial back pressure graph (PBPG) and show that the boundedness of a PBPG can be verified by checking the reachability in its strongly connected component graph (SCCG). Based on this, we formulate the problem of finding a minimum set of back pressure arcs (MBPA) and show that this problem can be reduced to the Minimum Cost Arborescence (MCA) problem for directed graphs. This allows us to obtain a polynomial time algorithm for synthesizing a minimum cost LIS implementation starting from a synchronous model of the original system. After adding back pressure arcs, we develop a localized Mixed Integer Linear Programming (LMILP) approach to optimize the throughput of the resulting LIS. This approach scales better than existing MILP-based throughput optimization techniques. In addition, we also provide an implementation of the LIS which refines its PBPG model. To the best of our knowledge, this is the first effort that considers the optimization of back pressure and throughput together in the design of latency insensitive systems.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2013.226