Novel Topologies for Symmetric, Asymmetric, and Cascade Switched-Diode Multilevel Converter With Minimum Number of Power Electronic Components

In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic...

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Bibliographic Details
Published in:IEEE transactions on industrial electronics (1982) 2014-10, Vol.61 (10), p.5300-5310
Main Authors: Shalchi Alishah, Rasoul, Nazarpour, Daryoosh, Hosseini, Seyed Hossein, Sabahi, Mehran
Format: Article
Language:English
Subjects:
Capacitors
Cascades
Converters
Driver circuits
Electric potential
Electronics
Insulated gate bipolar transistors
Logic gates
Multilevel
Switches
Topology
Voltage
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Summary:In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic switches against required voltage levels is a very important factor in designing of multilevel converter, because switches define the reliability, circuit size, cost, installation area, and control complexity. For asymmetric and cascade converter, new algorithms for determination of dc voltage sources values are presented. To produce maximum number of levels at the output voltage, the proposed cascade topology is optimized for different goals, such as the minimization of the number of power electronic switches, gate driver circuits, power diodes, dc voltage sources, and blocking voltage on switches. Comparison of the results of various multilevel converters will be investigated to reflect the merits of the presented topologies. The operations of the proposed multilevel converters have been analyzed with the experimental and simulation results for different topologies. Verification of the analytical results is done using MATLAB simulation.
ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2013.2297300