Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits

In this brief, a 1/10-rate bang-bang phase detector (BBPD) using a single edge-tracking clock and a phase interpolator (PI)-based clock and data recovery (CDR) circuit with the proposed BBPD is presented. While a typical 1/N-rate BBPD uses 2N clocks for data sampling and edge tracking, the proposed...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2014-04, Vol.61 (4), p.239-243
Main Authors: Kwak, Kang-Sub, Kwon, Oh-Kyong
Format: Article
Language:English
Subjects:
Bandwidth
Bang-bang phase detector (BBPD)
Circuits
clock and data recovery (CDR)
Clocks
CMOS
Data recovery
Data sampling
Delays
dual-loop CDR
Encoding
Jitter
Phase locked loops
Power consumption
Power demand
Product introduction
Semiconductors
single edge-tracking clock
Tracking
Voltage
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Summary:In this brief, a 1/10-rate bang-bang phase detector (BBPD) using a single edge-tracking clock and a phase interpolator (PI)-based clock and data recovery (CDR) circuit with the proposed BBPD is presented. While a typical 1/N-rate BBPD uses 2N clocks for data sampling and edge tracking, the proposed 1/N rate BBPD uses only N + 1 clocks, N for data sampling and 1 for edge tracking. The power consumption of the CDR with the proposed 1/N-rate BBPD is decreased. The reduction of the jitter tracking bandwidth of the CDR is compensated by the proposed data-encoding method. The 1/10-rate PI-based CDR with the proposed BBPD is implemented using a 0.18-μm CMOS process technology. The bit error ratio of less than 10 -12 is achieved at the effective data rate of 6.93 Gb/s using encoded 2 31 - 1 pseudorandom binary-sequence data inputs. The power consumption of the CDR is 29.4 mW at the supply voltage of 1.8 V and the active area is 0.117 mm 2 . The effective power efficiency of the CDR is 4.24 mW/Gb/s.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2014.2305012