Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements

We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87°C to 240°C, collector current density fixed at 400 kA/cm 2 , and collector-emitter voltage from 1.5 to 2.7 V)....

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Bibliographic Details
Published in:IEEE transactions on electron devices 2013-03, Vol.60 (3), p.1068-1074
Main Authors: Kone, G. A., Grandchamp, B., Hainaut, C., Marc, F., Labat, N., Zimmer, T., Nodjiadjim, V., Riet, M., Dupuy, J., Godin, J., Maneux, C.
Format: Article
Language:English
Subjects:
Accelerated aging test
Aging
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Engineering Sciences
Exact sciences and technology
Failure analysis
Heterojunction bipolar transistors
Indium phosphide
InP HBT
Integrated circuits
Junctions
Micro and nanotechnologies
Microelectronics
physical simulation TCAD
Resistance
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Stress
thermal resistance
Transistors
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Summary:We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87°C to 240°C, collector current density fixed at 400 kA/cm 2 , and collector-emitter voltage from 1.5 to 2.7 V). The physical origins of these failure mechanisms have been investigated using TCAD simulation. It points out the emitter sidewalls, the base-emitter junction periphery, and the emitter access resistance. Through three device generations, the analysis pointed out the successive technological enhancements to reduce the thermal resistance R TH and subsequently decrease the self-heating, leading to minimizing the impact of failure mechanisms.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2013.2241067