Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band k p Hamiltonian w...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2012-08, Vol.59 (8), p.2085-2092
Main Authors: Conzatti, F., Pala, M. G., Esseni, D., Bano, E., Selmi, L.
Format: Article
Language:English
Subjects:
Applied sciences
Chemical Sciences
Cross-disciplinary physics: materials science
rheology
Electronics
Engineering Sciences
Exact sciences and technology
InAs
Indium arsenides
Logic gates
Material chemistry
Materials
Materials science
Mathematical models
Micro and nanotechnologies
Microelectronics
MOSFETs
Nanomaterials
Nanoscale materials and structures: fabrication and characterization
Nanostructure
Nanowires
non-equilibrium Green's functions
Performance enhancement
Phonons
Physics
Quantum wires
Scattering
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Strain
Stress
Studies
Transistors
Tunnel-FET
Tunnels (transportation)
{\bf k} \cdot {\bf p}
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Summary:This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band k p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of I on with a small degradation of the subthreshold slope, as well as large improvements in the I off versus I on tradeoff for low I off and V DD values. Hence, an important widening of the range of I off and V DD values where tunnel FETs can compete with strained silicon MOSFETs is obtained.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2012.2200253