Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive doubl...

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Bibliographic Details
Published in:PloS one 2020-02, Vol.15 (2), p.e0228343-e0228343
Main Authors: Balasubramanian, P, Maskell, D L, Mastorakis, N E
Format: Article
Language:English
Subjects:
Adding circuits
Arrays
Asynchronous transfer mode
Backup software
CMOS
Complementary metal oxide semiconductors
Computer and Information Sciences
Computer engineering
Computer science
Custom design
Cycle time
Data processing
Delay
Design
Design optimization
Digital signal processing
Digital signal processors
Electrical Equipment and Supplies
Engineering and Technology
Equipment Design
Information processing
Mathematics
Multiplication
Multiplication & division
Multipliers
Physical Sciences
Power (Philosophy)
Production management
Signal processing
Technology
Time
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Summary:Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.
ISSN:1932-6203
1932-6203
DOI:10.1371/journal.pone.0228343