A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory

This paper explores the scalability of in-plane and perpendicular MTJ based STT-MRAMs from 65 nm to 8 nm while taking into consideration realistic variability effects. We focus on the read and write performances of a STT-MRAM based cache rather than the obvious advantages such as the denser bit-cell...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2013-02, Vol.48 (2), p.598-610
Main Authors: Ki Chul Chun, Hui Zhao, Harms, Jonathan D., Tae-Hyoung Kim, Jian-Ping Wang, Kim, Chris H.
Format: Article
Language:English
Subjects:
Anisotropic magnetoresistance
Applied sciences
Cache
Circuit properties
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
macromodel
magnetic tunnel junction (MTJ)
Magnetic tunneling
Magnetoelectric, magnetostrictive, magnetoacoustic, magnetooptic and magnetothermal devices. Spintronics
Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits
Random access memory
Resistance
roadmap
scalability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
spin torque transfer (STT)
Stability analysis
STT-MRAM
Thermal factors
Thermal stability
variability
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Summary:This paper explores the scalability of in-plane and perpendicular MTJ based STT-MRAMs from 65 nm to 8 nm while taking into consideration realistic variability effects. We focus on the read and write performances of a STT-MRAM based cache rather than the obvious advantages such as the denser bit-cell and zero static power. An accurate MTJ macromodel capturing key MTJ properties was adopted for efficient Monte Carlo simulations. For the simulation of access devices and peripheral circuitries, ITRS projected transistor parameters were utilized and calibrated using the MASTAR tool that has been widely used in industry. 6T SRAM and STT-MRAM arrays were implemented with aggressive assist schemes to mimic industrial memory designs. A constant J C 0·RA/VDD scaling scenario was used which to the first order gives the optimal balance between read and write margins of STT-MRAMs. The thermal stability factor ensuring a 10 year retention time was obtained by adjusting the free layer thickness as well as assuming improvement in the crystalline anisotropy. Our studies based on the proposed scaling methodology show that in-plane STT-MRAM will outperform SRAM from 15 nm node, while its perpendicular counterpart requires further innovations in MTJ material in order to overcome the poor write performance scaling from 22 nm node onwards.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2012.2224256