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Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX
Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ...
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| Published in: | IEEE electron device letters 2012-03, Vol.33 (3), p.348-350 |
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| Main Authors: | , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c293t-a98851f0cd18a391de9e5ac0dc544058cf475a3305e20807db0bfdf8e9024dc23 |
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| cites | cdi_FETCH-LOGICAL-c293t-a98851f0cd18a391de9e5ac0dc544058cf475a3305e20807db0bfdf8e9024dc23 |
| container_end_page | 350 |
| container_issue | 3 |
| container_start_page | 348 |
| container_title | IEEE electron device letters |
| container_volume | 33 |
| creator | Ohata, A. Bae, Y. Fenouillet-Beranger, C. Cristoloveanu, S. |
| description | Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO 2 interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling. |
| doi_str_mv | 10.1109/LED.2011.2181816 |
| format | article |
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We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO 2 interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2011.2181816</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Back gate ; CMOS integrated circuits ; Design. Technologies. Operation analysis. Testing ; Electronic equipment and fabrication. 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We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO 2 interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling.</description><subject>Applied sciences</subject><subject>Back gate</subject><subject>CMOS integrated circuits</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>High K dielectric materials</subject><subject>Integrated circuits</subject><subject>Interfaces</subject><subject>Logic gates</subject><subject>mobility</subject><subject>MOSFET</subject><subject>MOSFETs</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon on insulator technology</subject><subject>silicon-on-insulator (SOI)</subject><subject>thin buried oxide (BOX)</subject><subject>Threshold voltage</subject><subject>Transistors</subject><subject>ultrathin film</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><recordid>eNo9kM1PwkAQxTdGExG9m3jZi8fizH6026NgRRJITYDordlut7JaCunuhf_eEgiZw0xm3nvJ_Ah5RBghQvoyz95GDBBHDFVf8RUZoJQqAhnzazKARGDEEeJbcuf9LwAKkYgB-VzsSte4cKBZu9GtsVvbBloe6Fibv2iqg6Vjp71rf6hr6boJnQ6bflrmM7rIl-_ZytMvFzZ0ddyO8-97clPrxtuHcx-SdS-afETzfDqbvM4jw1IeIp0qJbEGU6HSPMXKplZqA5WRQoBUphaJ1JyDtAwUJFUJZV3VyqbARGUYHxI45Zpu531n62Lfua3uDgVCcSRS9ESKI5HiTKS3PJ8se-2Nbuqu_9f5i49JGQslk173dNI5a-3lHKNgAIr_A8fLZ4k</recordid><startdate>20120301</startdate><enddate>20120301</enddate><creator>Ohata, A.</creator><creator>Bae, Y.</creator><creator>Fenouillet-Beranger, C.</creator><creator>Cristoloveanu, S.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20120301</creationdate><title>Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX</title><author>Ohata, A. ; Bae, Y. ; Fenouillet-Beranger, C. ; Cristoloveanu, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-a98851f0cd18a391de9e5ac0dc544058cf475a3305e20807db0bfdf8e9024dc23</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Applied sciences</topic><topic>Back gate</topic><topic>CMOS integrated circuits</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>High K dielectric materials</topic><topic>Integrated circuits</topic><topic>Interfaces</topic><topic>Logic gates</topic><topic>mobility</topic><topic>MOSFET</topic><topic>MOSFETs</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon on insulator technology</topic><topic>silicon-on-insulator (SOI)</topic><topic>thin buried oxide (BOX)</topic><topic>Threshold voltage</topic><topic>Transistors</topic><topic>ultrathin film</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ohata, A.</creatorcontrib><creatorcontrib>Bae, Y.</creatorcontrib><creatorcontrib>Fenouillet-Beranger, C.</creatorcontrib><creatorcontrib>Cristoloveanu, S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ohata, A.</au><au>Bae, Y.</au><au>Fenouillet-Beranger, C.</au><au>Cristoloveanu, S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2012-03-01</date><risdate>2012</risdate><volume>33</volume><issue>3</issue><spage>348</spage><epage>350</epage><pages>348-350</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO 2 interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2011.2181816</doi><tpages>3</tpages></addata></record> |
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| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 2012-03, Vol.33 (3), p.348-350 |
| issn | 0741-3106 1558-0563 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_25564857 |
| source | IEEE Electronic Library (IEL) Journals |
| subjects | Applied sciences Back gate CMOS integrated circuits Design. Technologies. Operation analysis. Testing Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology High K dielectric materials Integrated circuits Interfaces Logic gates mobility MOSFET MOSFETs Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon on insulator technology silicon-on-insulator (SOI) thin buried oxide (BOX) Threshold voltage Transistors ultrathin film |
| title | Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX |
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