Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX

Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ...

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Bibliographic Details
Published in:IEEE electron device letters 2012-03, Vol.33 (3), p.348-350
Main Authors: Ohata, A., Bae, Y., Fenouillet-Beranger, C., Cristoloveanu, S.
Format: Article
Language:English
Subjects:
Applied sciences
Back gate
CMOS integrated circuits
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
High K dielectric materials
Integrated circuits
Interfaces
Logic gates
mobility
MOSFET
MOSFETs
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon on insulator technology
silicon-on-insulator (SOI)
thin buried oxide (BOX)
Threshold voltage
Transistors
ultrathin film
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Summary:Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO 2 interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2011.2181816