Shielding Methodologies in the Presence of Power/Ground Noise

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enh...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2011-08, Vol.19 (8), p.1458-1468
Main Authors: Kose, Selçuk, Salman, Emre, Friedman, Eby G.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
Circuit properties
Coupling capacitance
Coupling circuits
Crosstalk
crosstalk noise
crosstalk reduction techniques
Design engineering
Design. Technologies. Operation analysis. Testing
dI/dt noise
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Grounds
Inductance
Insertion
Integrated circuit interconnections
Integrated circuit noise
Integrated circuit technology
Integrated circuits
interconnect
Joining
Miscellaneous
mutual inductance
Noise
Noise reduction
power/ground (P/G) noise
Semiconductor device noise
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
shield insertion
Shielding
Shields
spacing
Studies
Very large scale integration
Voltage
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Description
Summary:Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enhance signal integrity due to increased P/G noise coupling on the victim line. A 2π RLC interconnect model is used to investigate the effects of both coupling capacitance and mutual inductance on the crosstalk noise. Physical spacing and shield insertion are compared in terms of the coupling noise on the victim line for several technology nodes. Boundary conditions are also provided to determine the effective range of spacing and shield insertion in the presence of P/G noise. Additionally, the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2010.2054119