A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface

This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns ran...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2008-01, Vol.43 (1), p.132-140
Main Authors: Villa, C., Vimercati, D., Schippers, S., Polizzi, S., Scavuzzo, A., Perroni, M., Gaibotti, M., Sali, M.L.
Format: Article
Language:English
Subjects:
Algorithms
Applied sciences
Architecture
Circuit properties
Circuits
Clocks
Data structures
DDR interface
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Flash memory
Flash memory (computers)
Hardware
Integrated circuits
Integrated circuits by function (including memories and processors)
multilevel flash
NOR flash memory
Operational amplifiers
Paper technology
Programming
Random access
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Throughput
Time domain analysis
Voltage
Wireless communication
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Description
Summary:This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2008.916028