Loading…
Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell
A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface orig...
Saved in:
| Main Authors: | , , , , , , , , , |
|---|---|
| Format: | Conference Proceeding |
| Language: | English |
| Subjects: | |
| Online Access: | Request full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| cited_by | |
|---|---|
| cites | |
| container_end_page | 830 |
| container_issue | |
| container_start_page | 827 |
| container_title | |
| container_volume | |
| creator | KIM, Il-Gweon KIM, Nam-Sung CHOI, Se-Kyeong YOUN, Tae-Un JUNG, Hyuck-Chai KWEON, Jae-Soon CHUN, Young-Il KIM, Wan-Soo BONG, Myung-Jong PARK, Joo-Seog |
| description | A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface originating from ILD-contained hydrogen and moisture. In addition, on the basis of the hydronium-like model, five process schemes to overcome the anomalous edge channel effect, are independently suggested: (1) outgassing prior to stopper Si/sub 3/N/sub 4/, (2) cutting off migration path (3) using high temperature oxide (HTO) as gate inner sidewall (SW) spacer, (4) Si-rich high density plasma (HDP) process and (5) incorporating the appropriate quantity of fluorine during the ILD HDP process. |
| doi_str_mv | 10.1109/IEDM.2002.1175965 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>pascalfrancis_6IE</sourceid><recordid>TN_cdi_pascalfrancis_primary_15785931</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1175965</ieee_id><sourcerecordid>15785931</sourcerecordid><originalsourceid>FETCH-LOGICAL-i205t-918520a0a02962abc726891edd3fe4cb74fcdba7aa325a00c45236565728b0373</originalsourceid><addsrcrecordid>eNpFkE9LxDAQxQMiKGs_gHjJRdBD1_xpmua47K5a6CKKnpdpMt1GYlnSXvrtDVRw3sDjMT8GZgi55WzNOTNP9X53WAvGRIpamVJdkMzoiqWWuigFvyLZOH6zVNIU0qhr8l4PE8YAM0bqPAa0U_SWPtTN7jGPGGBCR9GdkNoehgEDxa5LEPUD7f2ppw6H0U8z3X1sDtRiCDfksoMwYvbnK_L1vP_cvubN20u93TS5F0xNueGVEgyShCkFtFaLsjIcnZMdFrbVRWddCxpACgWM2UIJWapSaVG16Ry5IvfL3jOMFkIXYbB-PJ6j_4E4H7nSlTKSJ-5u4Twi_o-XB8lfca1ZSA</addsrcrecordid><sourcetype>Index Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>KIM, Il-Gweon ; KIM, Nam-Sung ; CHOI, Se-Kyeong ; YOUN, Tae-Un ; JUNG, Hyuck-Chai ; KWEON, Jae-Soon ; CHUN, Young-Il ; KIM, Wan-Soo ; BONG, Myung-Jong ; PARK, Joo-Seog</creator><creatorcontrib>KIM, Il-Gweon ; KIM, Nam-Sung ; CHOI, Se-Kyeong ; YOUN, Tae-Un ; JUNG, Hyuck-Chai ; KWEON, Jae-Soon ; CHUN, Young-Il ; KIM, Wan-Soo ; BONG, Myung-Jong ; PARK, Joo-Seog</creatorcontrib><description>A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface originating from ILD-contained hydrogen and moisture. In addition, on the basis of the hydronium-like model, five process schemes to overcome the anomalous edge channel effect, are independently suggested: (1) outgassing prior to stopper Si/sub 3/N/sub 4/, (2) cutting off migration path (3) using high temperature oxide (HTO) as gate inner sidewall (SW) spacer, (4) Si-rich high density plasma (HDP) process and (5) incorporating the appropriate quantity of fluorine during the ILD HDP process.</description><identifier>ISBN: 9780780374621</identifier><identifier>ISBN: 0780374622</identifier><identifier>DOI: 10.1109/IEDM.2002.1175965</identifier><language>eng</language><publisher>Piscataway NJ: IEEE</publisher><subject>Annealing ; Applied sciences ; Design. Technologies. Operation analysis. Testing ; Dielectrics ; Electronics ; Etching ; Exact sciences and technology ; Hydrogen ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Plasma applications ; Plasma density ; Plasma temperature ; Random access memory ; Research and development ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Threshold voltage</subject><ispartof>Digest. International Electron Devices Meeting, 2002, p.827-830</ispartof><rights>2004 INIST-CNRS</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1175965$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,783,787,792,793,2065,4059,4060,27939,55250</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1175965$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=15785931$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>KIM, Il-Gweon</creatorcontrib><creatorcontrib>KIM, Nam-Sung</creatorcontrib><creatorcontrib>CHOI, Se-Kyeong</creatorcontrib><creatorcontrib>YOUN, Tae-Un</creatorcontrib><creatorcontrib>JUNG, Hyuck-Chai</creatorcontrib><creatorcontrib>KWEON, Jae-Soon</creatorcontrib><creatorcontrib>CHUN, Young-Il</creatorcontrib><creatorcontrib>KIM, Wan-Soo</creatorcontrib><creatorcontrib>BONG, Myung-Jong</creatorcontrib><creatorcontrib>PARK, Joo-Seog</creatorcontrib><title>Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell</title><title>Digest. International Electron Devices Meeting</title><addtitle>IEDM</addtitle><description>A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface originating from ILD-contained hydrogen and moisture. In addition, on the basis of the hydronium-like model, five process schemes to overcome the anomalous edge channel effect, are independently suggested: (1) outgassing prior to stopper Si/sub 3/N/sub 4/, (2) cutting off migration path (3) using high temperature oxide (HTO) as gate inner sidewall (SW) spacer, (4) Si-rich high density plasma (HDP) process and (5) incorporating the appropriate quantity of fluorine during the ILD HDP process.</description><subject>Annealing</subject><subject>Applied sciences</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dielectrics</subject><subject>Electronics</subject><subject>Etching</subject><subject>Exact sciences and technology</subject><subject>Hydrogen</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Plasma applications</subject><subject>Plasma density</subject><subject>Plasma temperature</subject><subject>Random access memory</subject><subject>Research and development</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Threshold voltage</subject><isbn>9780780374621</isbn><isbn>0780374622</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpFkE9LxDAQxQMiKGs_gHjJRdBD1_xpmua47K5a6CKKnpdpMt1GYlnSXvrtDVRw3sDjMT8GZgi55WzNOTNP9X53WAvGRIpamVJdkMzoiqWWuigFvyLZOH6zVNIU0qhr8l4PE8YAM0bqPAa0U_SWPtTN7jGPGGBCR9GdkNoehgEDxa5LEPUD7f2ppw6H0U8z3X1sDtRiCDfksoMwYvbnK_L1vP_cvubN20u93TS5F0xNueGVEgyShCkFtFaLsjIcnZMdFrbVRWddCxpACgWM2UIJWapSaVG16Ry5IvfL3jOMFkIXYbB-PJ6j_4E4H7nSlTKSJ-5u4Twi_o-XB8lfca1ZSA</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>KIM, Il-Gweon</creator><creator>KIM, Nam-Sung</creator><creator>CHOI, Se-Kyeong</creator><creator>YOUN, Tae-Un</creator><creator>JUNG, Hyuck-Chai</creator><creator>KWEON, Jae-Soon</creator><creator>CHUN, Young-Il</creator><creator>KIM, Wan-Soo</creator><creator>BONG, Myung-Jong</creator><creator>PARK, Joo-Seog</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>IQODW</scope></search><sort><creationdate>2002</creationdate><title>Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell</title><author>KIM, Il-Gweon ; KIM, Nam-Sung ; CHOI, Se-Kyeong ; YOUN, Tae-Un ; JUNG, Hyuck-Chai ; KWEON, Jae-Soon ; CHUN, Young-Il ; KIM, Wan-Soo ; BONG, Myung-Jong ; PARK, Joo-Seog</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i205t-918520a0a02962abc726891edd3fe4cb74fcdba7aa325a00c45236565728b0373</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Annealing</topic><topic>Applied sciences</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Dielectrics</topic><topic>Electronics</topic><topic>Etching</topic><topic>Exact sciences and technology</topic><topic>Hydrogen</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Plasma applications</topic><topic>Plasma density</topic><topic>Plasma temperature</topic><topic>Random access memory</topic><topic>Research and development</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, Il-Gweon</creatorcontrib><creatorcontrib>KIM, Nam-Sung</creatorcontrib><creatorcontrib>CHOI, Se-Kyeong</creatorcontrib><creatorcontrib>YOUN, Tae-Un</creatorcontrib><creatorcontrib>JUNG, Hyuck-Chai</creatorcontrib><creatorcontrib>KWEON, Jae-Soon</creatorcontrib><creatorcontrib>CHUN, Young-Il</creatorcontrib><creatorcontrib>KIM, Wan-Soo</creatorcontrib><creatorcontrib>BONG, Myung-Jong</creatorcontrib><creatorcontrib>PARK, Joo-Seog</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, Il-Gweon</au><au>KIM, Nam-Sung</au><au>CHOI, Se-Kyeong</au><au>YOUN, Tae-Un</au><au>JUNG, Hyuck-Chai</au><au>KWEON, Jae-Soon</au><au>CHUN, Young-Il</au><au>KIM, Wan-Soo</au><au>BONG, Myung-Jong</au><au>PARK, Joo-Seog</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell</atitle><btitle>Digest. International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2002</date><risdate>2002</risdate><spage>827</spage><epage>830</epage><pages>827-830</pages><isbn>9780780374621</isbn><isbn>0780374622</isbn><abstract>A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface originating from ILD-contained hydrogen and moisture. In addition, on the basis of the hydronium-like model, five process schemes to overcome the anomalous edge channel effect, are independently suggested: (1) outgassing prior to stopper Si/sub 3/N/sub 4/, (2) cutting off migration path (3) using high temperature oxide (HTO) as gate inner sidewall (SW) spacer, (4) Si-rich high density plasma (HDP) process and (5) incorporating the appropriate quantity of fluorine during the ILD HDP process.</abstract><cop>Piscataway NJ</cop><pub>IEEE</pub><doi>10.1109/IEDM.2002.1175965</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9780780374621 |
| ispartof | Digest. International Electron Devices Meeting, 2002, p.827-830 |
| issn | |
| language | eng |
| recordid | cdi_pascalfrancis_primary_15785931 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Annealing Applied sciences Design. Technologies. Operation analysis. Testing Dielectrics Electronics Etching Exact sciences and technology Hydrogen Integrated circuits Integrated circuits by function (including memories and processors) Plasma applications Plasma density Plasma temperature Random access memory Research and development Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Threshold voltage |
| title | Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-11-15T10%3A32%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Interlayer%20dielectric%20(ILD)-related%20edge%20channel%20effect%20in%20high%20density%20DRAM%20cell&rft.btitle=Digest.%20International%20Electron%20Devices%20Meeting&rft.au=KIM,%20Il-Gweon&rft.date=2002&rft.spage=827&rft.epage=830&rft.pages=827-830&rft.isbn=9780780374621&rft.isbn_list=0780374622&rft_id=info:doi/10.1109/IEDM.2002.1175965&rft_dat=%3Cpascalfrancis_6IE%3E15785931%3C/pascalfrancis_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i205t-918520a0a02962abc726891edd3fe4cb74fcdba7aa325a00c45236565728b0373%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1175965&rfr_iscdi=true |