Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell

A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface orig...

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Main Authors: KIM, Il-Gweon, KIM, Nam-Sung, CHOI, Se-Kyeong, YOUN, Tae-Un, JUNG, Hyuck-Chai, KWEON, Jae-Soon, CHUN, Young-Il, KIM, Wan-Soo, BONG, Myung-Jong, PARK, Joo-Seog
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Applied sciences
Design. Technologies. Operation analysis. Testing
Dielectrics
Electronics
Etching
Exact sciences and technology
Hydrogen
Integrated circuits
Integrated circuits by function (including memories and processors)
Plasma applications
Plasma density
Plasma temperature
Random access memory
Research and development
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Threshold voltage
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Summary:A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface originating from ILD-contained hydrogen and moisture. In addition, on the basis of the hydronium-like model, five process schemes to overcome the anomalous edge channel effect, are independently suggested: (1) outgassing prior to stopper Si/sub 3/N/sub 4/, (2) cutting off migration path (3) using high temperature oxide (HTO) as gate inner sidewall (SW) spacer, (4) Si-rich high density plasma (HDP) process and (5) incorporating the appropriate quantity of fluorine during the ILD HDP process.
DOI:10.1109/IEDM.2002.1175965