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PVT Compensation for Wilkinson Single-Slope Measurement Systems

A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2012-10, Vol.59 (5), p.2444-2450
Main Authors: Tham, K. V., Ulaganathan, C., Nambiar, N., Greenwell, R. L., Britton, C. L., Ericson, M. N., Holleman, J., Blalock, B. J.
Format: Article
Language:English
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Summary:A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5- μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2012.2212722