Vertical Interconnections by Electroless Pd Atoms on Immersion Au Surface for Heterogeneous Integration

Electroless Pd atoms were employed to bond vertical interconnection for chip-stacking applications without pressure and at a temperature below 100 °C. Vertical interconnections were created by channeling an electroless Pd plating solution through microchannels, enabling the reduced Pd atoms to assem...

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Bibliographic Details
Published in:Journal of the Electrochemical Society 2024-07, Vol.171 (7), p.72502
Main Authors: Shih, Po-Shao, Huang, Jeng-Hau, Gräfner, Simon Johannes, Kao, Chin-Li, Lin, Yung-Sheng, Hung, Yun-Ching, Kao, C. R.
Format: Article
Language:English
Subjects:
3D integration
electroless plating
low-temperature bonding
microfluidic system
pressure free bonding
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Summary:Electroless Pd atoms were employed to bond vertical interconnection for chip-stacking applications without pressure and at a temperature below 100 °C. Vertical interconnections were created by channeling an electroless Pd plating solution through microchannels, enabling the reduced Pd atoms to assemble naturally within the gaps between two opposing Cu pillars. Notably, the Pd deposition resulted in epitaxial growth along the orientation of the Cu pillar surface, suggesting improved electrical properties for future high-frequency applications. In this study, highly uniform electroless Pd-bonded Cu pillar joints were fabricated using a patterned microfluidic system. The required bonding time was significantly correlated with the plating temperature. Furthermore, the electroless Pd-bonded joints exhibit a robust strength of approximately 55 MPa. Pd exhibits greater skin depth than other plating materials, which helps reduce signal loss and latency during high-frequency signal transmission. This innovative approach offers promise as a potential candidate for future 5G applications requiring low bonding stress and minimal thermal budget.
ISSN:0013-4651
1945-7111
DOI:10.1149/1945-7111/ad5c07