Vertically Integrated ZRAM toward Extremely Scaled Memory

This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with sti...

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Main Authors: Lee, Byung-Hyun, Ahn, Dae-Chul, Kang, Min-Ho, Jeon, Seung-Bae, Bang, Tewook, Bae, Hagyoul, Park, Jun-Young, Hong, Dae-Won, Park, Nam-Soo, Choi, Yang-Kyu
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with stiction-free stability and process simplicity, vertical integration of multiple silicon nanowire was achieved with high uniformity and high reproducibility. Finally, high performance suitable for further scaling was presented in zero-capacitor DRAM (ZRAM) operable with up to five-story SiNW channels without sacrificing scalability.
ISSN:1938-5862
1938-6737
DOI:10.1149/07505.0311ecst