Deterministic Frequency and Voltage Enhancements on the POWER10 Processor

Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability V_{\mathrm {DDMAX}} . These combine with a runtime algorithm for workload optimized frequenc...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2023-01, Vol.58 (1), p.102-110
Main Authors: Vanderpool, Brian, Restle, Phillip J., Fluhr, Eric, Still, Gregory, Campisano, Francesco A., Charmichael, Ian, Marz, Eric, Batra, Rahul, Willaman, Richard
Format: Article
Language:English
Subjects:
Algorithms
Characterization
Clocks
computer
determinism
digital droop sensor (DDS)
droop
dynamic voltage and frequency scaling (DVFS)
Electric potential
Frequency measurement
IBM
Indexes
microprocessor
Microprocessors
overvolting
power management
Temperature measurement
Temperature sensors
Throttling
Time-frequency analysis
undervolting
VMAX
Voltage
Voltage control
voltage regulator
Workload
workload optimized frequency (WOF)
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Summary:Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability V_{\mathrm {DDMAX}} . These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltage.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2022.3225378