HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks

SRAM based computing-in-memory (SRAM-CIM) techniques have been widely studied for neural networks (NNs) to solve the "Von Neumann bottleneck". However, as the scale of the NN model increasingly expands, the weight cannot be fully stored on-chip owing to the big device size (limited capacit...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-11, Vol.69 (11), p.4465-4474
Main Authors: Zhang, He, Liu, Junzhan, Bai, Jinyu, Li, Sai, Luo, Lichuan, Wei, Shaoqian, Wu, Jianxin, Kang, Wang
Format: Article
Language:English
Subjects:
Artificial neural networks
Computation
Computational modeling
Computing-in-memory (CIM)
Data transfer (computers)
Dynamic random access memory
Efficiency
Energy
Energy consumption
Flash memory (computers)
Load modeling
Loading
MRAM
Network latency
Neural networks
neural networks (NNs)
Random access memory
SRAM
Static random access memory
System-on-chip
Transistors
Weight reduction
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:SRAM based computing-in-memory (SRAM-CIM) techniques have been widely studied for neural networks (NNs) to solve the "Von Neumann bottleneck". However, as the scale of the NN model increasingly expands, the weight cannot be fully stored on-chip owing to the big device size (limited capacity) of SRAM. In this case, the NN weight data have to be frequently loaded from external memories, such as DRAM and Flash memory, which results in high energy consumption and low efficiency. In this paper, we propose a hybrid-device computing-in-memory (HD-CIM) architecture based on SRAM and MRAM (magnetic random-access memory). In our HD-CIM, the NN weight data are stored in on-chip MRAM and are loaded into SRAM-CIM core, significantly reducing energy and latency. Besides, in order to improve the data transfer efficiency between MRAM and SRAM, a high-speed pipelined MRAM readout structure is proposed to reduce the BL charging time. Our results show that the NN weight data loading energy in our design is only 0.242 pJ/bit, which is 289 \times less in comparison with that from off-chip DRAM. Moreover, the energy breakdown and efficiency are analyzed based on different NN models, such as VGG19, ResNet18 and MobileNetV1. Our design can improve \mathbf {58\times \,\,to\,\,124\times } energy efficiency.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2022.3199440