An Optimal Design for 1.2kV 4H-SiC JBSFET (Junction Barrier Schottky Diode Integrated MOSFET) With Deep P-Well

This letter reports the demonstration of 1.2 kV 4H-SiC Schottky-integrated MOSFETs (JBSFETs) achieving the same specific on-resistance as the pure MOSFET by using an innovative layout approach as well as novel deep P-well structure. The proposed JBSFET significantly reduces the specific on-resistanc...

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Bibliographic Details
Published in:IEEE electron device letters 2022-05, Vol.43 (5), p.785-788
Main Authors: Kim, Dongyoung, Jang, Seung Yup, DeBoer, Skylar, Morgan, Adam J., Sung, Woongje
Format: Article
Language:English
Subjects:
channeling implantation
Circuit design
deep P-well
design approach
Engineering
JBSFETs
JFETs
Layout
Layouts
Leakage current
Leakage currents
MOSFET
MOSFETs
Schottky barriers
Schottky contact
Schottky diodes
Short circuits
short-circuit
SiC
Silicon carbide
specific on-resistance
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Summary:This letter reports the demonstration of 1.2 kV 4H-SiC Schottky-integrated MOSFETs (JBSFETs) achieving the same specific on-resistance as the pure MOSFET by using an innovative layout approach as well as novel deep P-well structure. The proposed JBSFET significantly reduces the specific on-resistance accomplishing 2x reduction in the chip size, when compared with the traditional, chip-to-chip parallel connection of separate MOSFET and JBS diode. Moreover, the leakage current originated from the Schottky contact was successfully suppressed by adopting a 1.8~\mu \text{m} deep P-well structure implemented by channeling implantation. Device design strategy with layout approach, fabrication, and static and short-circuit characteristics are discussed in this letter. In order to understand and clarify the experimental results, 2D simulations were conducted.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2022.3162156