A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a syst...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2021-09, Vol.68 (9), p.3182-3186
Main Authors: Sarmiento, Marco, Nguyen, Khai-Duy, Duran, Ckristian, Hoang, Trong-Thuc, Serrano, Ronaldo, Hoang, Van-Phuc, Tran, Xuan-Tu, Ishibashi, Koichiro, Pham, Cong-Kha
Format: Article
Language:English
Subjects:
Beat sensor
Bias
Circuits
Energy harvesting
Field programmable gate arrays
Instruction sets (computers)
Internet of Things
IoT
low-power
Microcontrollers
Microprocessors
Open8
Power consumption
Power demand
Power management
Radio frequency
Random access memory
Read-only memory devices
Registers
Silicon
SOTB
Stability
Static random access memory
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Summary:For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- \mu \text{W} 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2021.3090102