SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms

This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technolo...

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Bibliographic Details
Published in:IEEE access 2021, Vol.9, p.75446-75459
Main Authors: Biondi, Alessandro, Casini, Daniel, Cicero, Giorgiomaria, Borgioli, Niccolo, Buttazzo, Giorgio, Patti, Gaetano, Leonardi, Luca, Bello, Lucia Lo, Solieri, Marco, Burgio, Paolo, Olmedo, Ignacio Sanudo, Ruocco, Angelo, Palazzi, Luca, Bertogna, Marko, Cilardo, Alessandro, Mazzocca, Nicola, Mazzeo, Antonino
Format: Article
Language:English
Subjects:
Artificial neural networks
Computer architecture
Cryptography
Cyber-physical systems
embedded systems
Field programmable gate arrays
FPGA
Hardware
hypervisor
Linux
New technology
Real-time systems
Resource management
Safety
Subsystems
Switches
Traffic management
Virtual machine monitors
Virtualization
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Summary:This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2021.3080842