A 333-MHz dual-MAC DSP architecture for next-generation wireless applications

We introduce the first DSP core developed at the Analog Devices and Intel Joint DSP Development Center. The 16-bit fixed-point core combines some of the best features of traditional DSPs and micro-controllers and compares favorably with dual-MAC DSPs on DSP specific benchmarks and with micro-control...

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Bibliographic Details
Main Authors: Kolagotla, R.K., Fridman, J., Hoffman, M.M., Anderson, W.C., Aldrich, B.C., Witt, D.B., Allen, M.S., Dunton, R.R., Booth, L.A.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Convergence
Costs
Digital signal processing
Hardware
Pipelines
Random access memory
Registers
System buses
Throughput
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Summary:We introduce the first DSP core developed at the Analog Devices and Intel Joint DSP Development Center. The 16-bit fixed-point core combines some of the best features of traditional DSPs and micro-controllers and compares favorably with dual-MAC DSPs on DSP specific benchmarks and with micro-controllers on micro-controller specific benchmarks. In addition, the core supports a rich set of alignment independent packed byte instructions to enable an efficient implementation of 3G algorithms in next-generation wireless applications. The deep and fully interlocked pipeline allows the core to run at 333-MHz in the 0.18-/spl mu/m TSMC process.
ISSN:1520-6149
2379-190X
DOI:10.1109/ICASSP.2001.941089