The FPGA Hardware Implementation of the Gated Recurrent Unit Architecture

The long short-term memory (LSTM) is the most widely used recurrent neural network representation for modeling sequential data. However, it is assumed an expensive modeling architecture as it requires many hardware components to be implemented, which is inefficient in solving problems based on small...

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Bibliographic Details
Main Authors: Zaghloul, Zaghloul Saad, Elsayed, Nelly
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
deep learning
FPGA
Gated Recurrent Unit
GRU
Logic gates
LSTM
Power demand
Recurrent neural networks
Signal processing
Time series analysis
Training
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Summary:The long short-term memory (LSTM) is the most widely used recurrent neural network representation for modeling sequential data. However, it is assumed an expensive modeling architecture as it requires many hardware components to be implemented, which is inefficient in solving problems based on small datasets. Therefore, in this paper, we propose a novel hardware implementation of the Gated Recurrent Unit (GRU) as a smaller alternative recurrent structure of the LSTM. The GRU has a smaller structure than the LSTM, which simplifies hardware components' implementation and reduces overall power consumption. The proposed GRU hardware implementation can be perfectly fit problems that depend on small datasets.
ISSN:1558-058X
DOI:10.1109/SoutheastCon45413.2021.9401819