Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates

An architecture of rapid single-flux-quantum logic circuits using clockless gates is proposed. Compared with a circuit composed of only clocked gates, a circuit using clockless gates includes fewer clocked gates, and therefore, a smaller clock distribution network. A circuit in the proposed architec...

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Bibliographic Details
Published in:IEEE transactions on applied superconductivity 2021-06, Vol.31 (4), p.1-7
Main Authors: Kawaguchi, Takahiro, Takagi, Kazuyoshi, Takagi, Naofumi
Format: Article
Language:English
Subjects:
Adding circuits
clock distribution network
clockless logic gates
Clocks
Computer architecture
Delays
Gates (circuits)
Logic circuits
Logic design
Logic gates
Pipelines
Rapid single-flux-quantum (RSFQ) circuit
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Summary:An architecture of rapid single-flux-quantum logic circuits using clockless gates is proposed. Compared with a circuit composed of only clocked gates, a circuit using clockless gates includes fewer clocked gates, and therefore, a smaller clock distribution network. A circuit in the proposed architecture is constructed from pipeline stages. Each pipeline stage consists of a column of clocked gates and a succeeding block of clockless gates. The function of a pipeline register of a stage is implemented by the latching function of the clocked gates in the column. The combinational logic of a stage is implemented by the logic function of the clocked gates in the column and that of the clockless gates in the block. We designed a two-stage-pipelined 4-bit carry-lookahead-adder using clockless gates as a design example of the proposed architecture. It had reductions of the count of clocked gates and the area by 33 and 13%, respectively, compared with that composed of only clocked gates. The 4-bit adder in the proposed architecture was fabricated and demonstrated with the maximum clock frequency of 21.4 GHz and the bias margin of \pm16%.
ISSN:1051-8223
1558-2515
DOI:10.1109/TASC.2021.3068960