A low-cost CMOS time interval measurement core

A low-cost time interval measurement circuit with 0.5 ns measurable period is implemented in 0.35 /spl mu/m 2P4M CMOS technology; the architecture is based on dual-slope method. The main purpose is not only concentrated on the time-interval measurement, but also the setup/hold time measurement of re...

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Bibliographic Details
Main Authors: Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Clocks
CMOS technology
Integrated circuit measurements
Logic arrays
Operational amplifiers
Resistors
Switches
System-on-a-chip
Time measurement
Online Access:Request full text
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Summary:A low-cost time interval measurement circuit with 0.5 ns measurable period is implemented in 0.35 /spl mu/m 2P4M CMOS technology; the architecture is based on dual-slope method. The main purpose is not only concentrated on the time-interval measurement, but also the setup/hold time measurement of registers. The resolution of the proposed work is 1/16 clock period and can be extended to higher precision. In order to improve the minimal measurable time period, a settling time canceling method is proposed to force the charging procedure operated in linear region. The offset voltage of operational amplifier is also considered. The calibration of the measured results could be done easily by digital circuits.
DOI:10.1109/ISCAS.2001.922204