High quality ultra thin CVD HfO/sub 2/ gate stack with poly-Si gate electrode

We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface prope...

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Bibliographic Details
Main Authors: Lee, S.J., Luan, H.F., Bai, W.P., Lee, C.H., Jeon, T.S., Senzaki, Y., Roberts, D., Kwong, D.L.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Boron
CMOS technology
Electrodes
Hafnium oxide
High K dielectric materials
High-K gate dielectrics
Leakage current
MOSFETs
Thermal stability
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Summary:We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si gate. In addition, the HfO/sub 2/ gate stack is thermally stable in direct contact with n/sup +/-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ gate stack with p/sup +/-poly Si gate.
DOI:10.1109/IEDM.2000.904252