A Two-Step ADC With Statistical Calibration

This paper describes a prototype two-step ADC with adjustable resolution in 40 nm CMOS technology. It uses a front-end successive-approximation-register ADC and a back-end time-domain ADC. Digital statistical calibration overcomes errors from front-end mismatch as well as inter-stage and back-end no...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2020-08, Vol.67 (8), p.2588-2601
Main Authors: Yu, Yi-Long, Hurst, Paul J., Levy, Bernard C., Lewis, Stephen H.
Format: Article
Language:English
Subjects:
Calibration
Capacitors
CMOS
Delays
Histograms
Probability density function
Prototypes
Quantization (signal)
SAR ADC
statistical calibration
time-domain ADC
Two-step ADC
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Summary:This paper describes a prototype two-step ADC with adjustable resolution in 40 nm CMOS technology. It uses a front-end successive-approximation-register ADC and a back-end time-domain ADC. Digital statistical calibration overcomes errors from front-end mismatch as well as inter-stage and back-end nonlinearity by analyzing specific statistical properties. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2020.2978271