Variation-Resilient Design Techniques for Energy-Constrained Systems

Process, voltage, and temperature (PVT) variations substantially increase the variability of digital CMOS logics and reduce the operation robustness, especially for energy-constrained systems with aggressive voltage scaling. This paper reviews several variation-resilient design techniques for addres...

Full description

Saved in:
Bibliographic Details
Main Authors: Wu, Bing-Chen, Liu, Tsung-Te
Format: Conference Proceeding
Language:English
Subjects:
adaptive design
and temperature (PVT) variations
Clocks
Delays
Energy efficiency
Fully integrated voltage regulator
Pipeline processing
process
Sensors
variation-resilient techniques
voltage
Voltage control
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Process, voltage, and temperature (PVT) variations substantially increase the variability of digital CMOS logics and reduce the operation robustness, especially for energy-constrained systems with aggressive voltage scaling. This paper reviews several variation-resilient design techniques for addressing PVT variations to improve the energy efficiency of digital CMOS VLSI circuits. The scope includes static and adaptive design techniques for design-time and run-time optimization, respectively. In addition, an emerging adaptive design strategy combining the fully integrated voltage regulator for system-level optimization is also introduced.
ISSN:1942-9401
DOI:10.1109/IOLTS.2019.8854384