A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems

A new breed of Form-Factor-Driven DRAMs offers 80% lower standby power and > 50% IO signal reduction vs. Capacity-Driven commodity DRAM. Command/address/data are multiplexed onto 16 pins and combined with a Serial Control Pin in a Single-Edge-Pinout-Floorplan, providing bus efficiency >98%. Ma...

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Bibliographic Details
Main Authors: Shiah, C., Chang, C.N., Crisp, Richard, Lin, C.P., Pan, C.N., Chuang, C.P., Chen, H.L., Jheng, S.H., Chang, T.F., Huang, W.J., Ting, K.C., Dai, Rick, Huang, W.M., Rong, B.D., Lu, Nicky
Format: Conference Proceeding
Language:English
Subjects:
Arrays
Clocks
DRAM
Pins
Random access memory
Reduced-Pin-Count
Small-Form-Factor
Switches
Switching circuits
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Summary:A new breed of Form-Factor-Driven DRAMs offers 80% lower standby power and > 50% IO signal reduction vs. Capacity-Driven commodity DRAM. Command/address/data are multiplexed onto 16 pins and combined with a Serial Control Pin in a Single-Edge-Pinout-Floorplan, providing bus efficiency >98%. Major SOC-DRAM subsystem cost savings are enabled via die size, packaging and PCB area savings using this RPCA. A 100x speedup of array fills using a new Group Write circuit further reduces test cost.
ISSN:2158-5636
DOI:10.23919/VLSIC.2019.8778049