A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC

This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fab...

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Bibliographic Details
Main Authors: Seo, Min-Jae, Kim, Ye-Dam, Chung, Jae-Hyun, Ryu, Seung-Tak
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Capacitors
Frequency measurement
Gain
Interpolation
Linearity
Prototypes
Online Access:Request full text
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Summary:This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm 2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.
ISSN:2158-5636
DOI:10.23919/VLSIC.2019.8778005