Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS

This paper presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8-GS/s intermediate frequency (IF) sampling for a 1-GHz input bandwidth spanning from 1.5 to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove distortion resulting...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-05, Vol.66 (5), p.1758-1768
Main Authors: Tantawy, Ramy, Patel, Vipul J., Smith, Dale Shane, Rashid, S. M. Shahriar, Casto, Matthew, Duncan, Lucas, Fragasse, Roman, Dupaix, Brian, Boglione, Luciano, Goodman, Joel, Khalil, Waleed
Format: Article
Language:English
Subjects:
Amplifiers
Analog to digital conversion
Analog to digital converters
Bandwidth
BiCMOS
BiCMOS integrated circuits
Broadband
Buffers
Capacitors
channelized
Clamps
Clock drivers
Clocks
CMOS
Current mirrors
direct sampling
Distortion
distortion cancellation
Heterojunction bipolar transistors
High speed
Intermediate frequencies
Linearity
Power consumption
RF and mixed signal IC design
RF front ends
sample-and-hold
Sampling
sampling circuits
Semiconductor devices
SiGe
Silicon germanides
Silicon germanium
software-defined
track-and-hold
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8-GS/s intermediate frequency (IF) sampling for a 1-GHz input bandwidth spanning from 1.5 to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130-nm BiCMOS technology using SiGe heterojunction bipolar transistors to buffer and sample the wideband input. The proposed SHA enables monolithic integration with a high-speed analog-to-digital converter core to realize a high-performance converter solution. This independent sampling front end occupies a core chip area of 0.6 mm 2 and consumes an average power of 1.26 W. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers, a high-speed clock driver, and externally adjustable current mirror biases. The high-speed clock drivers and buffers add 170 mW to the total power consumption. The measurements of the fabricated SHA show a 10-bit effective resolution across the 1-GHz IF bandwidth and < −61-dBc HD 2 and HD 3 .
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2897991