Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10 −16 J, which is comparable to the binary equivalent...

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Bibliographic Details
Published in:IEEE electron device letters 2018-12, Vol.39 (12), p.1948-1951
Main Authors: Heo, Sunwoo, Kim, Sunmean, Kim, Kiyung, Lee, Hyeji, Kim, So-Young, Kim, Yun Ji, Kim, Seung Mo, Lee, Ho-In, Lee, Segi, Kim, Kyung Rok, Kang, Seokhyeong, Lee, Byoung Hun
Format: Article
Language:English
Subjects:
Adders
Adding circuits
CNTFETs
Doping
Equivalent circuits
Graphene
Graphene barristor
Inverters
Logic circuits
Logic gates
multi threshold voltage ternary graphene barristor
Multivalued logic
Power consumption
ternary full adder
ternary logic
Threshold voltage
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Summary:Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10 −16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-V th ternary graphene barristors.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2018.2874055