A CMOS-SOI Power Amplifier Technology using EDNMOS for Sub 6 GHz Wireless Applications

Technology benchmarking results specific to power amplifiers (PA) application designed using extended drain NMOS (EDNMOS) on SOI is presented. Improved kink free conductance characteristics of this device leads to superior performance when the optimized EDNMOS is used standalone as a PA output stage...

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Bibliographic Details
Main Authors: Toh, Rui Tze, Parthasarathy, Shyam, Zhang, Shaoqiang, Govindarajan, Madabusi, Wong, Jen Shuang, Chew, Kok Wai, Andia, Luis, Ang, Diing Shenp
Format: Conference Proceeding
Language:English
Subjects:
EDMOS
kink-effect
Logic gates
MOS devices
Performance evaluation
Power amplifiers
Radio frequency
RF power amplifier
silicon-on-insulator (SOI)
Transistors
Wireless communication
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Summary:Technology benchmarking results specific to power amplifiers (PA) application designed using extended drain NMOS (EDNMOS) on SOI is presented. Improved kink free conductance characteristics of this device leads to superior performance when the optimized EDNMOS is used standalone as a PA output stage or in a cascode arrangement with other faster devices. The CMOS technology with this device is a viable alternative for designing watt level power amplifier on SOI.
ISSN:2375-0995
DOI:10.1109/RFIC.2018.8429029