A 50 Mbit/s iterative turbo-decoder

Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive coding gains, turbo codes have been proposed for several applications, although they suffer a large decoding delay. This paper...

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Bibliographic Details
Main Authors: Viglione, F., Masera, G., Piccinini, G., Ruo Roch, R., Zamboni, M.
Format: Conference Proceeding
Language:English
Subjects:
Bit error rate
Clocks
Costs
Delay
Iterative decoding
Logic design
Performance gain
Signal to noise ratio
Throughput
Turbo codes
Online Access:Request full text
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Summary:Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive coding gains, turbo codes have been proposed for several applications, although they suffer a large decoding delay. This paper presents the design of a turbo decoder with high performances in terms of throughput implemented using TSPC (true single phase clocking) logic family. In order to achieve the best compromise between cost (in terms of area) and throughput, several architectural solutions have been analyzed. The whole system and in particular its core, the SISO module, has been verified through VHDL simulations. HSPICE simulations show that the system can operate with a 1 GHz clock and thus it can reach a throughput of 50 Mbit/s.
DOI:10.1109/DATE.2000.840035