A New Approach for VDMOSFETs' Gate Oxide Degradation Based on Capacitance and Subthreshold Current Measurements Under Constant Electrical Stress

In this brief, we proposed a new gate oxide degradation model for vertical double diffused MOS devices under constant electrical stress. To form a complete model, we separated the changes associated with gate oxide and Si-SiO 2 interface. We presented oxide trap-induced gate oxide and interface trap...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2018-04, Vol.65 (4), p.1650-1652
Main Authors: Sezgin-Ugranli, Hatice Gul, Ozcelep, Yasin
Format: Article
Language:English
Subjects:
Capacitance
Capacitance measurement
Degradation
Electron traps
gate oxide breakdown
Logic gates
Mathematical model
modeling
MOS devices
Scanning electron microscopy
Silicon
Silicon dioxide
Stress
Stresses
vertical double diffused MOSFET (VDMOSFET)
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Summary:In this brief, we proposed a new gate oxide degradation model for vertical double diffused MOS devices under constant electrical stress. To form a complete model, we separated the changes associated with gate oxide and Si-SiO 2 interface. We presented oxide trap-induced gate oxide and interface trap-induced Si-SiO 2 interface degradation effects on the model, separately. We used capacitance measurements for gate oxide and subthreshold current measurements for Si-SiO 2 interface degradation. We presented the survive of the stress-induced gate oxide and interface capacitances during stress time. We also expressed the mathematical expressions for parts of the proposed model.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2018.2808162