Sub-60 nm physical gate length SOI CMOS

This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design is...

Full description

Saved in:
Bibliographic Details
Main Authors: Yang, I.Y., Chen, K., Smeys, P., Sleight, J., Lin, L., Leong, M., Nowak, E., Fung, S., Maciejewski, E., Varekamp, P., Chu, W., Park, H., Agnello, P., Crowder, S., Assaderaghi, F., Su, L.
Format: Conference Proceeding
Language:English
Subjects:
Boron
CMOS technology
Copper
Design optimization
Dielectric substrates
Implants
Parasitic capacitance
Research and development
Silicon on insulator technology
Threshold voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of silicon film thickness. A high performance SOI CMOS with well-behaved 52 nm gate length devices is demonstrated.
DOI:10.1109/IEDM.1999.824186